1. Field of the Invention
Example embodiments of the present invention relate generally to a multi-level cell (MLC) memory device and method thereof, and more particularly to a multi-level cell (MLC) memory device configured to perform data operations and method thereof.
2. Description of Related Art
Conventional Single-Level Cell (SLC) memory may store single-bit data in a single memory cell. Thus, a SLC memory may be referred to as a single bit cell (SBC).
FIG. 1 illustrates a cell threshold voltage in a conventional SLC memory. As shown in FIG. 1, single-bit data may be stored and read at different voltages or “distributions”. Referring to FIG. 1, two distributions may be divided by a threshold voltage, denoted by a vertical dotted line in FIG. 1, programmed in a memory cell. For example, if a voltage from 0.5 volts to 1.5 volts is read from the memory cell, data stored in the memory cell may be interpreted as a first logic level (e.g., a higher logic level or logic “1”). If a voltage from 2.5 volts to 3.5 volts is read from the memory cell, data stored in the memory cell may be interpreted as a second logic level (e.g., a lower logic level or logic “0”). Data stored in the memory cell may be classified based on a difference between cell currents or cell voltages during a data read operation.
A conventional Multi-Level Cell (MLC) memory may be more highly integrated than an SLC. MLC memory may also be referred to as a multi-bit cell (MBC) memory. However, as a number of bits stored in a single memory cell increases, a reliability of the stored memory may decrease, and a read failure rate may increase. If m bits are stored in a single memory cell, 2m number of distributions (e.g., separate voltage ranges for each associated bit) may be formed. However, because a voltage window associated with each distribution may be limited, a threshold voltage difference between neighboring bits may decrease and a read failure rate may increase as m increases. Therefore, it may be difficult to increase a storage density of a conventional MLC memory.